In the data processing arts, it has been a consistent goal to achieve faster and faster computing rates. Coupled with this goal of faster computing rates is a parallel goal of providing system architecture that provides for a general purpose computing operation. In the past, it has been common for the data processing system to have system architecture designed for a fixed data word length. Often, the data word length is selected to be compatible with the data word storage register capacity in the main memory system. For example, if a 36-bit memory registers are employed, it was often common that the data processing systems would function on a 36-bit basis. At a relatively early time in the development of binary computing systems, it was recognized that a more efficient utilization of the main memory could be accomplished by providing for half-word access to the main memory system for reading and writing operations. Such systems usually operated on a whole-word basis in arithmetic operations, even though access could be made to the memory on a half-word basis.
As system architecture and memory systems were further improved and refined, systems were developed that permitted access for reading and writing in the main memory selectively on the basis of quarter-words, third-words as well as half-words on a fixed bit-arrangement basis. Since the binary data processing systems were normally arranged with the memory register capacity being fixed at some multiple of two or some power of two, these fractional arrangements were relatively easy to define and implement. With the development of the fractional-word reading and writing capability in memory systems, there was developed various types of data processing architectures that permitted the arithmetic manipulation of fractional data words.
In the types of data processing systems mentioned thus far, no provision was made for providing the capability of writing variable length bit-fields, where the bit-field length could vary anywhere from a single bit in any memory word position, to the extent of writing a full memory word. Further, the systems were limited to fractional recording within the confines of a single addressed memory register, and word boundary crossing was not possible.
As the binary data processing systems were developed by various manufacturers, each manufacturer established individually designed system architectures, including establishment of various standards for memory register word capacity. For example, one manufacturer would have developed a product line where a 24-bit memory register word capacity was essentially a standard for its equipment, while another manufacturer would have developed a line of equipment where a 36-bit memory register was a standard for its equipment. The various systems that were of a general purpose variety would include instruction repertoires that differed in their specific functions, from system to system, but collectively often-times could be programmed to accomplish the same functions as other systems. As equipment costs became ever-more expensive, it became desireable from a customer view point that there be some form of compatibility between systems provided by different manufacturers. One important element in providing data processing systems that can accomplish performance of functions that are system compatible with other data processing systems, without limiting the memory register capacity to a fixed memory word capacity, is to provide a memory accessing system that allows for writing variable data bit-fields that can be utilized to emulate the memory register word capacity of other data processing systems. If the data processing system is to be utilized to emulate a system having a data word capacity less than the emulating system, and the writing of a variable bit-field is limited to a single word in the memory, there would result an inefficiency of utilization of the memory since it is likely that the unused bit positions could be effectively utilized.
As data processing systems became more complex, and the word capacity was increased, the fractional-word writing resulted in inefficiencies of utilization of memory, and failed to provide adequate versatility for many data processing operations where it was desireable to manipulate variable-length bit arrangements.
Many logical and data manipulative operations require the ability to read and write various variable length bit-fields. Such operations are often accomplished by logical instructions coupled with shifting of data words to accomplish the insertion of variable bit-fields in data words to be recorded. The sequences of logical operations coupled with shifting are time consuming and in many systems require additional shifting circuitry.